1. Field of the Invention
This invention relates to a process for manufacturing multilayer printed circuit boards. Another aspect of this invention relates to printed circuit boards manufactured by the process of this invention.
2. Prior Art
Many methods are known for the preparation of multilayer printed circuits. In many older techniques conductive holes are introduced through printed circuit boards to accommodate insertion and soldering of electrical component leads and for making electrical connections between two or more circuit patterns. Holes are conventionally drilled or punched through a copper clad, rigid board followed by a plating procedure, e.g., a copper reduction procedure such as that disclosed in "Printed Circuits Handbook" edited by Clyde F. Coombs, Jr., published by McGraw-Hill Book Company, New York, NY, 1967, Chapter 5. The copper clad board with plated through-holes can then be processed into printed circuit boards using resists and processes disclosed in "Printed Circuits Handbook", supra or in U.S. Pat. No. 3,469,982. A disadvantage of the conventional copper reduction procedure for plating holes is a waste of expensive catalyst which adheres not only to the hole walls but to the copper cladding, resulting in superfluous overplating of the copper cladding.
The preparation of multilayered printed circuit boards using a photohardenable film and additive plating process is described in U.S. Pat. Nos. 4,054,479 and 4,054,483. The conductive interconnections between the layers are produced by predrilling holes in a photosensitive element and registering the holes with underlying printed circuit patterns Such predrilling procedures by their inherent inaccuracies of registration are limited to printed circuit patterns where circuit lines are not closely spaced.
U.S. Pat. No. 4,157,407 describes a process for preparing printed circuits with electrical interconnections without drilling or punching the requisite hole and without using the time consuming hole chemical catalyzation process of the prior art. Multilayered circuits can be provided by this process which have high packing density with multiple crossovers and interconnections or vias. The process of U.S. Pat. No. 4,157,407, while effective for the preparation of multilayered circuits, requires many repetitive steps in practical use including two registrations of the image and exposure to actinic radiation; two applications of finely divided metal, including application to the through-holes; two applications of heat; and two removals of excess metal particles, e.g., by water-wash followed by drying.
U.S. Pat. No. 4,469,777 describes a process for preparing a two layer printed circuit having conductive interconnections wherein at least one layer of a photo-adhesive composition is applied to a substrate bearing an electrically conductive circuit pattern and exposing said photoadhesive layer or layers through a circuit image of three different optical densities, i e , zero, gray and opaque, removing portions of the photosensitive layer by solvent washout, applying finely divided metal, alloy or plating catalyst to adherent image areas, optionally curing the printed circuit, e g., heating or ultraviolet exposure and plating to form an interconnected electrically conductive circuit pattern U.S. Pat. No. 4,469,777 states that multilayer printed circuits can also be prepared by repeating the steps using additional layers of photoadhesive material.
U.S. Pat. No. 3,934,335 describes a process in which multilayer printed circuit boards are fabricated by coating a suitable substrate, metal, plastic paper, with a photosensitive coating, exposing the photo-sensitive coating to form a dielectric thereof, coating the dielectric layer with a coating of a photosensitive chemical solution, selectively imaging and developing the photosensitive coating to form a desired circuit pattern on the dielectric coating, forming a first layer of circuitry by coating the circuit pattern with a conducting material, coating the circuitry bearing layer with a second layer of photosensitive material, selectively exposing and developing the second layer of photosensitive material to form a dielectric with open windows to the first circuit layer, coating the second dielectric layer of the first circuitry with a coating of photosensitive chemical solution, selectively imaging and developing the coating of photosensitive chemical solution to form a circuit pattern and an interconnect pattern and forming a conductor layer of circuitry and interconnects, the interconnect metallization connecting the second circuitry layer with the first circuitry layer, repeating the process to form additional circuitry layers to perform a desired electrical function and forming on the last dielectric layer a metallization such as either a solder mask for circuit terminals or a ground plane and thereafter either retaining the substrate if desired as for example, a heat sink or additional support or both, or removing the substrate to form a very light weight multilayer printed circuit board.
U.S. Pat. No. 4,159,222 describes the method of manufacturing printed circuitry with sufficiently high resolution to permit line densities of at least 1 mil lines on 3 mil centers includes the steps of placing a thickness of dry film photoresist on a smooth, polished substrate or carrier optionally, applying a thin lubricating layer of spray wax to the exposed surface of the photoresist, wringing a mask defining a desired conductive circuit pattern into high integrity, intimate contact with the surface of the resist, exposing and developing the resist to remove the resist from the smooth surface in regions where the conductive circuit pattern is to be formed, electroplating the conductors within the voids formed in the resist; removing all remaining resist, laminating a flowable dielectric material to the smooth surface of the substrate and the conductive circuit pattern, and removing the laminate material and conductive circuit pattern from the smooth surface.
U.S. Pat. No. 4,159,222 also states that if desired, conductive via interconnects can be selectively formed and additional layers of circuit patterns can be formed atop the first high resolution layer.
U.S. Pat. No. 4,306,925 describes a process for the manufacture of high density printed circuits by forming a first conductive circuit pattern on a polished temporary substrate, forming a second conductive circuit pattern (which may be an interconnect pattern) on the first pattern if desired, laminating a flowable insulator material to the first and second conductive circuit layers and temporary substrate to form first and second insulator layers, sanding to form a smooth top surface coplanar with the top of the top conductive pattern, selectively adding additional layers and a substrate and stripping the printed circuit from the temporary substrate. The conductive patterns may be formed with high resolution using photolithographic techniques.